1. Field of the Invention
The present invention relates to systems for the high speed generation and detection of error checking sequences for use in the transmission of telecommunications data. More particularly, the invention relates to a system for generating a cyclic redundancy code word which is appendend to the end of a transmitted message thus forming a frame check sequence to be transmitted. The frame check sequence is verified at the receiver to determine if any errors have occured in the transmission process.
2. Discussion of the Prior Art
Frame check sequence generators and frame check sequence testers are used to implement cyclic redundancy codes (CRC) for the purpose of detecting errors in telecommunications data. Advances in technology, especially in the digital telecommunications area, has created a need for exchanging large volumes of data at an ever increasing rate. This situation has created a need for faster frame check sequence generators and frame check sequence testers.
There are numerous examples of CRC generator/testers available in medium scale integrated (MSI) circuit packages in a variety of technologies. These CRC generator/testers are capable of implementing any of the standard CRC polynomials. The basic operation of these devices includes dividing the input data or message by one of the standard CRC polynomials and appending the resulting remainder to the message as check bits. At the receiver, the message plus check bits are divided by the same polynomial. If no error exists, the division results in a zero remainder.
The prior art frame check sequence generator/testers use a combination of shift registers and discrete combinational logic gates. The difficulty, especially at high data rates, with these types of circuits is that they require an amount of processing time, at a minimum, equal to a bit duration for each transmitted bit which often causes extensive delays in transmitting large amounts of data. The time delay is present because each bit is shifted serially into the CRC generator/tester at the same time that the data is being transmitted on the interconnecting medium. The same delay exists at the receiver because similar processing is necessary on the received data as was performed on the input data to generate the transmitted CRC.